1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device, and more particularly, to a method for forming a capacitor of a semiconductor device that prevents characteristic of a device from being deteriorated due to residue resulting from a process step of defining a storage node.
2. Background of the Related Art
Generally, in a process for fabricating a DRAM capacitor based on an electrochemical deposition (ECD) Pt process, a SiON film is deposited on a dummy pattern layer to improve a profile of a dummy pattern for defining a storage node.
The SiON film acts as an etching barrier film to facilitate a vertical profile of the dummy pattern. To remove the dummy pattern formed after the ECD Pt process, the SiON film is removed by a dry etching process.
A related art method for forming a capacitor of a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1A to 1E are sectional views illustrating related art process steps of forming a capacitor of a semiconductor device. FIG. 2A is a photograph showing a storage node after etch-back of an etching barrier film, and FIG. 2B is a photograph showing a storage node after wet deep-out of a dummy pattern.
As shown in FIG. 1A, an insulating film 11 and a surface anti-reflecting film 12 are sequentially formed on a semiconductor substrate (not shown) in which a cell transistor (not shown) is formed. A contact hole is formed to connect a capacitor with one electrode of the cell transistor.
A doped polysilicon layer is deposited within the contact hole by a chemical vapor deposition (CVD) process. The doped polysilicon layer is then etched back to form a recess portion, so that a plug layer 13 is formed. A low resistance contact film 14 and a barrier film 15 are formed in the recess portion so as to reduce contact resistance between the plug layer 13 and the barrier film 15 which will be formed later.
The low resistance contact film 14 is formed in such a manner that a material such as Ti is deposited on a silicon (Si) and annealed to form TiSix, and some of Ti which is not reacted with Si is removed.
The barrier film 15 is formed on an entire surface including a portion where the low resistance contact film 14 is formed. The barrier film 15 is then flattened to remain on the low resistance contact film 14.
Subsequently, Pt is deposited on the entire surface to form a first metal layer 16 used as a seed layer.
As shown in FIG. 1B, a dummy pattern 17 for patterning of a storage node and an etching barrier film 18 are formed on the entire surface. SiON is used as the etching barrier film 18.
As shown in FIG. 1C, the dummy pattern 17 and the etching barrier film 18 are selectively etched by a photolithography process to define a lower electrode formation region 19.
As shown in FIG. 1D, a second metal layer 20 is formed using the first metal layer 16 exposed in the storage node formation region, i.e., in a portion where the dummy pattern 17 is removed, as a seed layer. The second metal layer 20 is formed by the ECD process.
As shown in FIG. 1E, the etching barrier film 18 is removed by a dry etching process and the dummy pattern 17 is removed by a wet deep-out process.
However, in the related art process as above, when SiON used as the etching barrier film 18 is dry etched, blanket etching is performed without using a photo mask. At this time, since a dry etching gas acts on an upper surface of a lower electrode of Pt, residue containing Pt is generated.
Such residue remains even after the wet deep-out of the dummy pattern. In this case, electrical characteristic of the device may be deteriorated. Photographs showing such residue are shown in FIGS. 2A and 2B. Referring to FIG. 2B, a large quantity of the residue generated during etch-back process of the etching barrier film remains.
However, the related art method for forming a capacitor of a semiconductor device has several problems.
When removing the etching barrier film used to obtain a vertical profile of the dummy pattern for defining the storage node, residue is generated. The residue remains even after the dummy pattern is removed, thereby deteriorating electrical characteristic of the device. Particularly, unevenness occurs when a BST dielectric layer is deposited. For this reason, capacitance between cells becomes uneven and loss of current partially occurs.
Accordingly, the present invention is directed to a method for forming a capacitor of a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for forming a capacitor of a semiconductor device that prevents characteristic of a device from being deteriorated due to residue resulting from a process step of defining a storage node.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for forming a capacitor of a semiconductor device includes the steps of forming an insulating film having a contact hole on a substrate, forming a conductive layer within the contact hole, forming a first metal layer on an entire surface including the conductive layer, forming a dummy pattern and an etching barrier film on the first metal layer, selectively etching the dummy pattern and the etching barrier film to form a lower electrode formation region, forming a second metal layer in the lower electrode formation region using the first metal layer as a seed layer, removing the etching barrier film and the dummy pattern and performing a wet cleaning process to remove residue resulting from removing the etching barrier film and the dummy pattern, and removing the exposed first metal layer to form a lower electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.